Shrinking process technology nodes, increasing chip complexity, more complicated design verification tasks, and shorter times-to-market have multiplied the difficulty of designing systems-on-a-chip (SoCs). It's not enough to design a chip that meets specifications ?that chip must also make a successful transition to a manufacturing environment. To meet this objective, an EDA tool vendor and a silicon foundry ?Cadence Design Systems and TSMC ?have combined their technologies and expertise to ease the complexities of SoC design, offering specific process-related design enhancements for improved manufacturability.
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NANO Corporate Newsletter
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